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HMC5983
Table 15: Data Output Z Registers A and B
DZRA7
(0)
DZRB7
(0)
DZRA6
(0)
DZRB6
(0)
DZRA5
(0)
DZRB5
(0)
DZRA4
(0)
DZRB4
(0)
DZRA3
(0)
DZRB3
(0)
DZRA2
(0)
DZRB2
(0)
DZRA1
(0)
DZRB1
(0)
DZRA0
(0)
DZRB0
(0)
Data Output Register Operation
When one or more of the output registers are read, new data cannot be placed in any of the output data registers until all
six data output registers are read. This requirement also impacts DRDY and RDY, which cannot be cleared until new
data is placed in all the output registers.
Status Register
The status register is an 8-bit read-only register. This register is used to indicate device status. SR0 through SR7
indicate bit locations, with SR denoting the bits that are in the status register. SR7 denotes the first bit of the data stream.
Table 16: Status Register
SR7
(0)
SR6
(0)
SR5
(0)
SR4
(0)
SR3
(0)
SR2
(0)
SR1
LOCK (0)
SR0
RDY(0)
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